(1) Field of the Invention
This invention relates to a nonvolatile semiconductor memory. More particularly, the invention relates to an integrated injection logic device (hereafter referred to as I.sup.2 L) having a nonvolatile memory function.
(2) Description of the Prior Art
The I.sup.2 L is a new logic device which was published in H. H. Benger and S. K. Wiedman: Merged-Transistor Logic (MTL)-A Low-Cost Bipolar Logic Concept; IEEE J. of SSC, sc-7, 5, p. 340-346 (1972, October), K. Hart and A. Slob: Integrated Injection Logic: A New Approach to LSI; IEEE J. of SSC, sc-7, 5, p. 346-351 (1972, October), etc. The I.sup.2 L is noted in points of permitting a high packing density, having a wide range of application, being compatible with conventional bipolar transistors, etc.
FIG. 1A shows an equivalent circuit of the I.sup.2 L, and FIG. 1B a sectional structure of the device. As shown in FIG. 1A, the I.sup.2 L is expressed as the combination of a common base type PNP transistor 11 and a common emitter type NPN transistor 12. The emitter I of the transistor 11 is usually called the "injector," and a power supply is connected to this terminal. The base B of the transistor 12 is made an input terminal, and the collectors C.sub.1 to C.sub.3 are made output terminals, thereby to derive outputs in the multi-collector system. As the transistor 12 an ordinary planar type transistor is used by inverting its emitter and collector, and the emitter E is grounded in common for the whole device. This situation is apparent from the sectional view of FIG. 1B, and a lateral transistor is employed as the PNP transistor 11, in which a P-type region (having, for example, an impurity concentration on the order of 10.sup.18 cm.sup.-3) 13 is the emitter, an N-type epitaxial-grown semiconductor layer (having, for example, an impurity concentration on the order of 10.sup.16 cm.sup.-3) 14 is the base and a P-type region (having, for example, an impurity concentration on the order of 10.sup.18 cm.sup.-3) 15 is the collector. On the other hand, the NPN transistor 12 is constructed in such a manner that each N-type region (having, for example, an impurity concentration on the order of 10.sup.20 cm.sup.-3 ) 16 is the collector, that the P-type region 15 is the base and that the N-type epitaxial-grown semiconductor layer (for example, N-type Si epitaxial layer) 14 is the emitter. An N.sup.+ -type buried layer 191 and an N.sup.+ -type region 192 (having, for example, an impurity concentration on the order of 10.sup..degree. cm.sup.-3) serve to lead out the common ground terminal. The region 192 serves to prevent the crosstalk between adjacent gates. It is called the "N.sup.+ -type collar," and it sometimes has a shallow region part besides a part contacting with the region 191 and surrounds the I.sup.2 L. Shown at 17 is an insulating film (of SiO.sub.2 or the like). Numeral 181 designates an injector electrode, numeral 182 a base electrode, numerals 183, 183' and 183" collector electrodes and numeral 184 a ground electrode, and they are made of Al or the like. Numeral 10 indicates a semiconductor substrate of the P-type conductivity, which is made of P-type Si or the like.
As apparent from the figure, the collector of the PNP transistor 11 and the base of the NPN transistor 12 are the identical P-type semiconductor region 15. The base of the PNP transistor 11 and the emitter of the NPN transistor 12 are the N-type epitaxial layer 14, which is common for the whole device.
The I.sup.2 L above stated is small in the device area which it occupies and low in its power dissipation. In addition, it is readily integrated on a monolithic semiconductor IC chip together with an analog circuit employing bipolar transistors. Therefore, it is being extensively employed.